As mass storage devices (MSDs) are continuously developed, each new generation of MSDs stores a greater amount of data in handheld systems than the previous generation of MSDs. These new MSDs include FLASH chips and built-in micro hard disks that may be hardwired or may be plugged into the handheld systems, and plug-in memory cards. The plug-in memory card may use a standard interface, such as, for example, secure digital (SD) interface specification, a MultiMedia Card (MMC) interface specification, or the serial peripheral interface (SPI) interface specification. The MSDs that may be hardwired, for example, the micro hard disk, may also use the SD, MMC, or SPI interface.
Generally, data may be transferred from external memory by, for example, a CPU, or microprocessor, to an internal input/output (I/O) buffer in the MSD, and the data in the I/O buffer may be written to the MSD. In this manner, the CPU may quickly transfer data that is to be written to the MSD and continue with other tasks while the MSD completes writing data to the buffer. Similarly, data that is to be read from the MSD may be read from the internal storage locations of the MSD and stored in the I/O buffer and the CPU may then read the buffered data.
For example, FLASH chips may store data in “pages” where each page may have the capability to store about 2 kilobytes (KB) of data. During a write cycle to a FLASH chip, a programming device, for example, a microprocessor, may sequentially send write commands, page addresses, page data, and program commands to the FLASH chip. The page data for the MSD may be stored in the I/O buffer of the MSD. The write cycle for each byte written to the I/O buffer may be as short as 35 nanoseconds (ns). However, programming the I/O buffer data to the memory array in the FLASH chip may take a longer time, for example, 1 millisecond (mS) per 2 KB page. While the data is being programmed or written to a memory array in a FLASH device, a response signal may be de-asserted by the FLASH device to indicate that it is busy. When the programming of the data in the I/O buffer is finished, the FLASH chip may assert the response signal to indicate that it is ready for further accesses. The CPU may poll the response signal to determine when further accesses may be made to the FLASH chip. The incident waste of CPU processing may be undesirable.
During a read cycle from a FLASH chip, the CPU may sequentially send out a read command, page address, and fetch command. The read command may indicate to the FLASH chips to fetch a page of data from the page address in the memory array to the I/O buffer. This may take, for example, 50 microseconds (μs) for the FLASH chip to fetch a byte of data from the memory array to the I/O buffer. During the fetch cycle, the FLASH chip may de-assert the response signal to indicate that it is busy. The CPU may poll the response signal to determine when further accesses may be made to the FLASH chip. The incident waste of CPU processing may be undesirable. After data is fetched into the I/O buffer, the CPU may read the data from the I/O buffer at a fast rate, for example, of 35 ns per byte.
The time that a FLASH chip may spend in programming the memory array in the FLASH chip and/or fetching data from the memory array may be wasted for the CPU if it must poll the FLASH chips to see when it has completed that task. Additionally, the MSDs may trade data integrity for storage capacity, and may depend on an error correction code (ECC) to aid in minimizing bit errors that may occur. In some FLASH chips, for example, 16 extra bytes may be allocated for the ECC for each 2 KB page. The 16-byte ECC may be sufficient to correct 24 bits of random errors in the 2 KB page. However, ECC generation during writes to the MSDs and correction during reads from the MSDs may be very computation intensive, and may further waste the CPU's processing resources.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.